1. Field of the Invention
The present invention relates to a semiconductor device. More specifically, the invention relates to a nonvolatile semiconductor memory device such as a flash memory, which includes memory cells formed of metal oxide semiconductor (MOS) transistors each having a double (stacked) gate structure.
2. Description of the Related Art
Flash electrically erasable and programmable read only memories (flash EEPROMs) have recently been well known as nonvolatile semiconductor memory devices that are capable of electrically rewriting (writing and erasing) data and suitable for high density and large capacity. The flash EEPROMs include memory cells of MOS transistors each having a double-gate structure in which a floating gate is provided between a silicon substrate and a control gate.
The nonvolatile semiconductor memory devices such as flash EEPROMs have the following problem. If the distance between adjacent memory cells in the word line direction is shortened, an interference effect occurs between the memory cells with increases in capacity coupling between adjacent floating gates. This problem deteriorates cell characteristics, such as write and erase characteristics of memory cells.
As a solution to the above problem, it can be thought that the distance between adjacent memory cells is lengthened by decreasing only the width of a floating gate in the word line direction without changing the design pitches of memory cells. However, a floating gate, which is opposed to a silicon substrate with a tunnel oxide film interposed therebetween, is decreased in sectional area if only it is decreased only in width. It is therefore feared that cell current will be reduced. With this solution, the problem with the deterioration of cell characteristics due to the interference effect between adjacent memory cells can be resolved, but a new problem that the reduction in cell current deteriorates the cell characteristics will occur.
The above new problem will become serious in a high-density, large-capacity NAND flash EEPROM such as a next-generation memory with 90 nm or less design rules and a multivalued memory for storing multivalued data.
As described above, the nonvolatile semiconductor memory devices are microfabricated more and more and likely to decrease in the distance between adjacent memory cells. They have required a technique capable of reducing an interference effect that occurs between adjacent memory cells with increases in capacity coupling between adjacent floating gates without decreasing cell current, and avoiding deteriorating cell characteristics due to the microfabrication.
In order to suppress the increase of capacity coupling between adjacent floating gates, there have been proposed methods of forming a recess in an element isolation insulating film provided between memory cells and then forming a control gate line (word line) in the recess. Of these methods, there is a method of reliably forming a control gate line in a recess of an element isolating insulation film even though an element isolation trench decreases in width to suppress the capacity coupling between floating gates (see, e.g., Jpn. Pat. Appln. KOKAI Publication 2005-85996). In the prior art devices, the floating gates are each formed of a single film having a uniform width, while the control gate line extends to a deep portion of the element isolating insulation film.